Показаны сообщения с ярлыком S3 wafer fab. Показать все сообщения
Показаны сообщения с ярлыком S3 wafer fab. Показать все сообщения

среда, 17 апреля 2019 г.

Samsung объявляет о завершении разработки технологии изготовления чипов по 5-нм техпроцессу, заметно опередив конкурентов





Samsung активно использует своё преимущество как первопроходца полупроводниковой литографии с применением сканеров EUV-диапазона. Пока конкуренты из TSMC только готовится начать использовать сканеры с длиной волны 13,5нм, адаптировав их для выпуска чипов в рамках второго поколения техпроцесса с нормами 7 нм, Samsung идёт дальше и заявляет о завершении разработки техпроцесса с проектными нормами 5нм. Более того, южнокорейский техногигант объявил о начале приёма заказов на выпуск 5-нм решений для производства на мультипроектных пластинах. Это означает, что Samsung готов принимать цифровые проекты чипов с указанными нормами и выпускать опытные партии рабочего 5-нм кремния.
Быстро перейти от предложения 7-нм техпроцесса с EUV на производство 5-нм решений (также с EUV) мэйджору отрасли помогло то обстоятельство, что Samsung сохранил совместимость проектных элементов (IP), инструментов проектирования и контроля. Кроме прочего это означает, что клиенты сэкономят средства на приобретение средств проектирования, тестирования и готовых IP-блоков. Наборы PDK для проектирования, методология (DM, design methodologies) и платформы автоматического проектирования EDA стали доступны ещё в рамках разработки чипов для 7-нм норм Samsung с EUV в 4-м квартале прошлого года. Все эти инструменты обеспечат разработку цифровых проектов также для техпроцесса 5нм с транзисторами FinFET.
По сравнению с 7-нм EUV-техпроцессом, который вендор запустил в октябре прошлого года, 5-нм техпроцесс обеспечит увеличение эффективности использования площади кристалла на 25% (при этом Samsung пока избегает прямых заявлений о снижении размеров площади кристалл на 25%, что оставляет ему пространство для манёвра). Также переход на 5-нм техпроцесс позволит либо снизить на 20% энергопотребление чипов, либо повысить на 10% производительность решений. Ещё одним бонусом станет сокращение числа фотомасок, которые необходимы для производства полупроводников.
Выпуском продукции с использованием сканеров EUV займётся предприятие Samsung Fab S3, которое расположено в городе Хвасон. Во 2-й половине текущего года вендор завершит строительство нового корпуса рядом с Fab S3, которое будет готово выпускать чипы с использованием EUV-техпроцессов в следующем году, говорится в официальном пресс-релизе южнокорейского техногиганта.

Samsung Successfully Completes 5nm EUV Development to Allow Greater Area Scaling and Ultra-low Power Benefits

Samsung Electronics makes major strides in EUV-based advanced nodes, including 7nm mass production and 6nm customer tape-out

Samsung Electronics, a world leader in advanced semiconductor technology, today announced that its 5-nanometer (nm) FinFET process technology is complete in its development and now is ready for customers’ samples. By adding another cutting-edge node to its extreme ultraviolet (EUV)-based process offerings, Samsung is proving once again its leadership in the advanced foundry market.
Compared to 7nm, Samsung’s 5nm FinFET process technology provides up to a 25 percent increase in logic area efficiency with 20 percent lower power consumption or 10 percent higher performance as a result of process improvement to enable us to have more innovative standard cell architecture.
In addition to power performance area (PPA) improvements from 7nm to 5nm, customers can fully leverage Samsung’s highly sophisticated EUV technology. Like its predecessor, 5nm uses EUV lithography in metal layer patterning and reduces mask layers while providing better fidelity.
Another key benefit of 5nm is that we can reuse all the 7nm intellectual property (IP) to 5nm. Thereby 7nm customers’ transitioning to 5nm will greatly benefit from reduced migration costs, pre-verified design ecosystem, and consequently shorten their 5nm product development.
As a result of the close collaboration between Samsung Foundry and its ‘Samsung Advanced Foundry Ecosystem (SAFE™)’ partners, a robust design infrastructure for Samsung’s 5nm, including the process design kit (PDK), design methodologies (DM), electronic design automation (EDA) tools, and IP, has been provided since the fourth quarter of 2018. Besides, Samsung Foundry has already started offering 5nm Multi Project Wafer (MPW) service to customers.
“In successful completion of our 5nm development, we’ve proven our capabilities in EUV-based nodes,” said Charlie Bae, Executive Vice President of Foundry Business at Samsung Electronics. “In response to customers’ surging demand for advanced process technologies to differentiate their next-generation products, we continue our commitment to accelerating the volume production of EUV-based technologies.”
In October 2018, Samsung announced the readiness and its initial production of 7nm process, its first process node with EUV lithography technology. The company has provided commercial samples of the industry’s first EUV-based new products and has started mass production of 7nm process early this year.
Also, Samsung is collaborating with customers on 6nm, a customized EUV-based process node, and has already received the product tape-out of its first 6nm chip.
Mr. Bae continued, “Considering the various benefits including PPA and IP, Samsung’s EUV-based advanced nodes are expected to be in high demand for new and innovative applications such as 5G, artificial intelligence (AI), high performance computing (HPC), and automotive. Leveraging our robust technology competitiveness including our leadership in EUV lithography, Samsung will continue to deliver the most advanced technologies and solutions to customers.”
Samsung foundry’s EUV-based process technologies are currently being manufactured at the S3-line in Hwaseong, Korea. Additionally, Samsung will expand its EUV capacity to a new EUV line in Hwaseong, which is expected to be completed within the second half of 2019 and start production ramp-up from next year.

5nm: A Catalyst of the Fourth Industrial Revolution and What It Means for Semiconductor Innovations

by Daewon Ha
Logic TD team, Semiconductor R&D Center, Samsung Electronics

This week, Samsung Electronics announced that its 5-nanometer(nm) FinFET process technology based on EUV lithography  is now ready for production. This is a remarkable accomplishment and testament to the capability of our colleagues at the S3 wafer fab in Hwaseong, Korea and their supply chain partners.
For me, what is most exciting about this milestone is that it highlights how far the semiconductor industry innovations have come today and provides a glimpse into the evolutions that will shape the industry of tomorrow.
Consider that the 5nm process is here in just six months after last October’s unveiling of the first commercial application of EUV in our 7nm process. It’s a rapid progress made possible in large part by running thousands of wafer layers through EUV exposure systems each week. Hands-on experience is the only way to ascend the EUV learning curve, and that body of knowledge is growing daily.
In the learning process, we’re seeing one of the biggest and broadest benefits of EUV – the simplification of design by moving away from increasingly complex multi-patterning lithography strategies. While still early, it’s increasingly clear that the reduced number of mask steps and more straightforward process is nothing short of a revolution for silicon designers. Sighs of relief will be heard as EUV will be seamlessly incorporated into the existing design architectures.
Samsung’s 5nm is the next step in the evolution of EUV. 5nm will be more efficient and feature new innovations including Samsung’s proprietary Smart Diffusion Break (SDB) transistor architecture. One of the most important aspects of 5nm is that it supports 25 percent area reduction and 10 percent performance improvement or 20 percent power reduction than 7nm.
Also, it will be largely design-rule compatible with the existing design of 7nm. Therefore, it is essentially a recharacterization of the technology, not redesign, which will substantially reduce time and the cost of implementation. This combination of technological advance and economic advantage is very much in line with a grand tradition of the semiconductor industry.
This merging of technological advancement and economic benefits is very much in line with the grand tradition in the semiconductor industry as well as technologies including 5G, AI, Connected & Automotive, Robot, etc. – constantly serving as a catalyst for the fourth industrial revolution, while simultaneously driving costs down. That’s why the evolution-moment of 5nm is, in its own unique way, as important as the innovation-moment of 7LPP.
Bringing EUV into production has been a long, challenging process. It required substantial investment of time, money, and human resources. While there were certainly moments of doubt along the way, we had to pursue our vision. The 5nm announcement offers compelling evidence for the value of the investment. As businesses from diverse fields including Foundry, Fabless, the Design House, Packaging, Tests, etc., the semiconductor ecosystem will grow stronger. This is a new chapter for the semiconductor industry, and we are excited to be part of the continued journey in innovation.